This invention relates to the field of computer memory circuits, and more specifically to a method for making reduced-size FLASH memory circuits, and to the resulting memory circuit.
Electrically erasable and programmable read only memory (EEPROM) techniques also implement non-volatile memory on integrated circuits. EEPROMs can be electrically programmed, erased, and reprogrammed. EEPROM devices are useful as non-volatile memory units in computers and other systems. EEPROM circuits can also be used in chips whose primary function is not just memory, but includes other logical or computation functions. One technique of implementing an EEPROM is by use of a floating gate tunneling oxide (FLOTOX) transistor. To create a FLOTOX transistor, a field-effect transistor (FET) having source, drain, substrate, and gate terminals is modified to electrically isolate (float) the gate. This polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d or xe2x80x9cpolyxe2x80x9d) floating gate is created over a thin insulating layer of silicon dioxide (tunnel oxide). A second polysilicon gate (control gate) is created above the floating gate. The floating gate and control gate are separated by an interpoly insulating layer. Since the floating gate is electrically isolated, any charge stored on the floating gate is trapped. Storing sufficient charge on the floating gate will create an inversion channel between source and drain of the FET. Thus, the presence or absence of charge on the floating gate can represent two distinct data values.
FLOTOX transistors are selectively programmed by transferring electronic charges through the thin gate oxide onto the floating gate by Fowler-Nordheim tunneling. With the substrate voltage held at ground, the control gate is raised to a sufficiently high positive voltage so that electrons are transferred from the substrate to the floating gate by tunneling through the insulating thin gate oxide. The tunneling process is reversible. The floating gate can be erased by grounding the control gate and raising the drain voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the drain terminal of the transistor by tunneling through the insulating gate oxide. The voltage applied to the control gate during programming is higher than the voltage applied to the drain during erasure because, while the erasure voltage is applied directly across the gate oxide, the programming voltage is applied to the control gate and capacitively coupled onto the floating gate.
The transistors can be selectively reprogrammed in the same manner as described above, since the tunneling process is nondestructive. The programming and erasure voltages which effect Fowler-Nordheim tunneling are higher than the voltages normally used in reading the memory. The Fowler-Nordheim tunneling effect is negligible at the lower voltages used in reading the memory, allowing a FLOTOX transistor to maintain its programmed state for years if subjected only to normal read cycles.
Since reprogrammable non-volatile memory is useful for DRAM die identification and reconfiguring and remapping defective DRAM memory cells, it is desired to implement EEPROM through floating gate transistor structures which are compatible with existing DRAM processing steps.
U.S. Pat. No. 5,723,375 assigned to the assignee of the present invention (and incorporated herein by reference) describes a floating-gate memory cell that can be used in a DRAM or EEPROM.
Other convention fabrication techniques yield circuits having relatively large EEPROM memory cell areas. What is needed is a circuit which has an EEPROM memory cell area having a reduced area, and a method for producing such a circuit. What is also needed is a circuit having two or more different gate-oxide thicknesses, and a method for producing such a circuit.
The present invention provides an electronic circuit that includes a first set of one or more transistors each having a gate dielectric of a first thickness, and a second set of one or more transistors each having a gate dielectric of a second thickness different than the first thickness. In one embodiment, the circuit provides non-volatile EEPROM data storage.
In one embodiment, the first thickness is thicker than the second thickness. An initial thickness of dielectric is grown on both a first chip area for the first set of transistors and a second chip area for the second set of transistors. The dielectric is then removed from only the second chip area. Then a first and second final thickness of dielectric is grown on the first and second chip areas, respectively. Thus two distinct thicknesses of dielectric are provided.
In one such embodiment, the first and second chip areas are substantially co-planar. For example, a gate oxide is grown on a substrate to two distinct thicknesses.
In another such embodiment, the gate dielectric of the second thickness is an oxide layer sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing, and is covered by a polysilicon floating gate, a polysilicon control gate, and an electrical insulator layer separating the polysilicon floating gate and the polysilicon control gate. In one such embodiment, the gate dielectric of the first thickness is a gate oxide sufficiently thick to prevent electrical breakdown at operating voltages, and is covered by a polysilicon transistor gate that was deposited during the step that deposited the polysilicon floating gate.
One embodiment further includes a floating-gate poly layer over the second dielectric layer, an inter-poly nitride layer over the floating-gate poly layer, a control-gate poly layer over the inter-poly nitride layer, and a tungsten-silicide (WSix) layer over the control-gate poly layer.
In one such embodiment, the second dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate. The stack is bounded by a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, and a drain end and a source end. The circuit further includes a nitride layer covering the first side from the inter-poly nitride layer to the first trench, a nitride layer covering the second side from the inter-poly nitride layer to the second trench, a nitride layer covering the drain end from the inter-poly nitride layer to the substrate, and a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
Another embodiment further includes a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end, a tungsten source contact formed substantially adjacent to the nitride layer covering the source end, and a tungsten gate contact formed to substantially contact the WSix layer. In one such embodiment, an aluminum-copper (AlCu) line is formed substantially in contact with the tungsten drain contact.
Another aspect of the present invention provides a method for fabricating an electronic circuit. The method includes forming a first dielectric layer on both a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors, removing the first dielectric layer from the second chip area but not from the first chip area; and forming a second dielectric layer on both the first chip area to be used for the first set of transistors and on the second chip area to be used for the second set of transistors.
In one such embodiment, the first dielectric layer is thicker than the second dielectric layer, and wherein the first dielectric is a gate oxide for signal transistors, and the second dielectric is a gate oxide for memory-cell storage transistors. In another such embodiment, the first and second chip areas are substantially co-planar. In still another embodiment, the second dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing. In yet another embodiment, the first dielectric layer is a gate oxide sufficiently thick to prevent electrical breakdown at operating voltages, and is covered by a polysilicon transistor gate that was deposited during the step that deposited the polysilicon floating gate.
In one such embodiment, the method also includes depositing a floating-gate poly layer over the second dielectric layer, depositing an inter-poly nitride layer over the floating-gate poly layer, depositing a control-gate poly layer over the inter-poly nitride layer, and depositing a tungsten-silicide (WSix) layer over the control-gate poly layer.
In another such embodiment, the method also includes etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the second dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer, etching the stack to form a drain end and a source end, depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench, depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench; depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate, and depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
In yet another such embodiment, the method also includes forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end, forming a tungsten source contact substantially adjacent to the nitride layer covering the source end, and forming a tungsten gate contact to substantially contact the WSix layer. In one such embodiment, the method also includes forming an aluminum-copper (AlCu) line substantially in contact with the tungsten drain contact.
Still another aspect of the present invention provides a method for fabricating an electronic circuit. This circuit has a substrate and a floating-gate stack on the substrate. The stack includes a gate oxide on the substrate and at least one poly layer on the gate oxide. This method includes etching a plurality of trenches through the stack and depositing a nitride spacer layer on sides of the trenches.
In one embodiment, the nitride spacer layer is deposited to isolate all sides of a floating gate poly layer. In another embodiment, a first plurality of substantially parallel trenches are etched through the stack into the substrate, the nitride spacer layer is deposited on sides of the first plurality of parallel trenches, then a second plurality of substantially parallel trenches are etched substantially perpendicular to the first plurality of substantially parallel trenches and then the nitride spacer layer is deposited on sides of the second plurality of parallel trenches.
In one embodiment, the stack includes two poly layers separated by an inter-poly dielectric layer, and the nitride spacer layer covers the sides of both poly layers and the sides of the inter-poly dielectric layer.
Yet another aspect of the present invention provides a method for fabricating an electronic circuit, the circuit having a substrate, a gate oxide on the substrate, a floating-gate poly layer on the gate oxide, an inter-poly nitride layer on the floating gate poly layer, a control-gate poly layer on the inter-poly nitride layer; a tungsten-silicide (WSix) layer on the control-gate poly layer, and a nitride cap layer on the WSix layer. This method includes etching a plurality of isolation trenches along a first direction through the stack into the substrate, depositing a nitride spacer layer on sides of the isolation trenches, further etching to remove the nitride cap and to further deepen the plurality of isolation trenches into the substrate, filling the isolation trenches with tetraethylorthosilicate (TEOS), covering an area of the circuit with planarized borophosphosilicate glass (BPSG), etching lines along a second direction substantially perpendicular to the isolation trenches, depositing a nitride spacer layer on sides of the lines. The method also includes covering the area of the circuit with a thin TEOS layer, covering the area of the circuit with planarized (BPSG), etching trenches through the TEOS layer between adjacent transistors to the substrate and on portions of adjacent transistor areas to the WSix layer, using an etch that does not substantially etch nitride, depositing a titanium and/or titanium nitride (ti-nitride) barrier layer, filling the trench with tungsten, chemical-mechanical polishing (CMP) to planarize and remove tungsten and upper portions of oxide, stopping near tops of the nitride spacers, covering with BPSG, etching contacts through contact areas, depositing ti-nitride barrier layer in the contact areas, depositing tungsten in the contact areas, and chemical-mechanical polishing (CMP) back the tungsten to leave only the tungsten in the contact areas, and depositing aluminum copper (ALCU), etching interconnects, and covering with a passivation layer.
Yet another aspect of the present invention provides a method for fabricating an electronic circuit on a wafer. This method includes depositing a dielectric layer on a substrate of the wafer, depositing a first poly gate layer over the dielectric layer, depositing an inter-poly dielectric layer over the first poly layer, depositing a second poly gate layer over the inter-poly nitride layer, and removing the inter-poly dielectric and the second poly gate layer from some but not all of the first poly gate layer. One such embodiment also includes depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed. In another such embodiment, a tungsten-silicide (WSix) layer is deposited over the second poly gate layer to reduce resistance.
The present invention thus provides a circuit for an EEPROM cell having a reduced-area footprint, and methods for fabricating such a circuit. The present invention also provides for fabricating a two-thickness gate oxide layer. The present invention also provides for fabricating a polysilicon layer that is used for a floating gate poly for some transistors (which also include another poly gate for control), and is used for a regular gate for other transistors.
In some embodiments, an information-handling system (such as, for example, a personal computer or a cellular telephone) includes a processor, a display unit, an input/output subsystem, and a data storage memory, all coupled together. The memory includes an electronic data storage circuit according to embodiments of the present invention, for example, as described above.